1. Field of the Disclosure
The present disclosure relates to a shift register, and more particularly, to a shift register which is capable of preventing leakage of charges at a set node which occurs when the duty ratio of a scan pulse is small, so as to normally output the scan pulse.
2. Discussion of the Related Art
A shift register outputs a plurality of scan pulses in order to sequentially drive gate lines of a display device, such as a liquid crystal display.
A scan pulse has a duty ratio that can be set appropriately according to a given driving condition. In particular, when the duty ratio of the scan pulse is smaller, a duration in which the scan pulse is kept low (referred to hereinafter as a low duration) is longer. As a result, in this low duration, the possibility that charges at a set node of a stage will be leaked is higher. For this reason, there may occur a problem that the scan pulse is not normally output in an output period of the stage.